1. Field of the Invention
The present invention relates to a method of forming a diffusion layer and a method of manufacturing a nonvolatile semiconductor memory device.
2. Description of the Related Art
FIG. 1 is a sectional view for generally explaining a Depletion layer formation at the edge of a gate which bias applies to both Gate and Drain. First, when a negative voltage V.sub.G is to be applied to a floating gate 52, and a positive voltage V.sub.D is to be applied to a drain region 59 to extract electrical charges from the floating gate 52 to the drain region, a depletion region 59a indicated by dotted lines is produced in an n.sup.+ -type diffusion layer, as shown in FIG. 1. An effective electric field between the floating gate 52 and the drain region 59 is weakened due to this depletion layer, decreasing an F-N tunnel current. Therefore, an F-N tunnel type memory requires an overlapping region between a heavily doped n.sup.+ -type diffusion layer and a floating gate of a polysilicon film where it is difficult to produce a depletion layer or the depletion layer is very small even if it is produced, i.e., a tunnel window for allowing an F-N tunnel current to flow. On the other hand, a band to band tunnel current flows through the n.sup.+ -type region of the drain edge on the n.sup.+ -p junction portion in the p-type semiconductor substrate 50 due to band bend caused by application of the voltages V.sub.G and V.sub.D. That is, an electric field is extremely strengthened in an interface region 59a near an oxide film, and band to band tunneling current flows. Due to this, hot holes etc. are generated and the holes are injected to the tunnel oxide film. This decreases the element reliability and degrades the element characteristics soon. Therefore, a technique of smoothing the concentration gradient at a junction edge, easily bending the band of a diffusion layer, and suppressing a band to band tunnel current is required. For this purpose, the DDD structure is formed in which the concentration of the drain edge of a memory cell is low.
FIG. 2 is a sectional view illustrating the structure of a floating gate type nonvolatile semiconductor memory cell having a conventional DDD structure. The common source type memory cell is of 2-poly type memory cell, in which electrical charges are extracted from a floating gate 112 to a common source portion 120, 119b. To suppress an inter-band tunnel current, after the drain portion 119a is formed as an n.sup.+ -type diffusion region, phosphorus (P) as an n.sup.- -type ion and arsenic (As) as an n.sup.+ -type ion are simultaneously implanted into a p-type semiconductor substrate 110. Thereafter, an n.sup.+ -type diffusion region 119b and an n.sup.- -type diffusion region 120 are formed by subsequent annealing using a difference between the diffusion rate of phosphorus (P) and that of arsenic (As), realizing the common source regions of the DDD structure. Reference numerals 110a denote channel regions; 111, first gate insulating films; 117, field oxide films for providing an element isolation region; 121, second gate insulating films; and 122, a control gate.
FIGS. 3A to 3C are schematic sectional views for explaining a method of manufacturing a floating gate type nonvolatile semiconductor memory cell having a conventional 1-poly type LDD (Lightly Doped Drain) structure. Generally, as shown in FIG. 3A, after a first gate insulating film 111 is formed on a p-type semiconductor substrate 110, a polysilicon film is deposited and etched to form a gate 112. Thereafter, n.sup.- -type ions are implanted into the p-type semiconductor substrate 110 via the first gate insulating film 111 by self-alignment using the gate 112 as a mask. Next, as shown in FIG. 3B, an oxide film is deposited and etched to form spacers 115. n.sup.+ -type ions are implanted into the p-type semiconductor substrate 110 using the gate 112 and the spacers 115 as masks. As shown in FIG. 3C, annealing is performed to form n.sup.+ -type diffusion regions 119 and n.sup.- -type diffusion regions 120, which constitute an LDD structure.
The current memory cell, however, is required for micropatterning. In the memory cell having the conventional DDD structure in FIG. 2, after the polysilicon film is etched to form the floating gate 112, phosphorus (P) and arsenic (As) are simultaneously ion-implanted and annealed. In diffusing arsenic (As) by this annealing, phosphorus (P) is excessively diffused into the channel region, causing a short channel. For this reason, the conventional method is not suitable for micropatterning a memory cell.
According to the conventional general LDD formation method, for example, as shown in FIG. 3C, the n.sup.+ -type diffusion regions 119 reach only the end portions of the floating gate 112 consisting of the polysilicon film. The overlap between the floating gate 12 and the n.sup.+ -type diffusion regions 119 is not sufficient to operate the memory cell with a Fowler-Nordheim (to be referred to as F-N hereinafter) tunnel current. For this reason, movement of electrical charges between the source region and the floating gate is delayed, and the write/read/erase functions of the memory cell are degraded in an early stage.